1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a method of forming source/drain regions in semiconductor devices using multiple spacers.
2. Description of the Related Art
In general, memory devices, such as dynamic random access memory (DRAM), have many source/drain devices, for example, MOS transistor. In the conventional fabrication of the transistor for memory device, after the gate is formed on a semiconductor substrate, such as a silicon substrate, ion implantation is performed on the substrate to form source/drain regions. However, with increased integration of integrated circuits (ICs), the size of transistors must be reduced. Unfortunately, when the channel length of the transistors is less than 2 xcexcm, hot carrier effect, short channel effect, and punchthrough, well known issues between the source and drain regions, can degrade reliability. In other words, the electrical properties of MOS transistors significantly influence the performance of memory devices. In order to improve these problems, lightly doped drain (LDD) method and anti-punchthrough implantation, such as pocket implanting, are usually adopted in the conventional fabrication of transistors.
Such memory devices typically include a memory array region and a memory peripheral region (support or logic region). Each region includes source/drain devices, such as MOS transistors. In general, when the line space (the distance between gates) on the memory peripheral region is larger (about 1xcx9c2 xcexcm), the LDD implantation and anti-punchthrough implantation can be finished easily due to a larger process window for lithography. However, with increased integration of ICs the gate line width is shrunk less than 0.2 xcexcm and the gate line space is shrunk less than 0.4 xcexcm. Therefore, the fabrication of LDD and pocket implantation regions becomes more difficult due to the limitation of lithography.
Accordingly, an object of the invention is to provide a novel and simple method of forming source/drain regions in a semiconductor device to adjust the dimension of the doping regions using three stacked spacers as masks, thereby forming the required doping regions.
According to one aspect, the invention provides a method of forming source/drain regions in a semiconductor device. First, a substrate having at least one gate structure covered by a capping layer is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the capping layer and the third insulating spacer as masks to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the capping layer and the second insulating spacer as masks to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the capping layer and the first insulating spacer as masks to form third doping regions, thereby preventing punchthrough.
The capping layer and the first insulating spacer can be silicon nitride. The second insulating spacer can be high-density plasma (HDP) oxide, and the third insulating spacer can be silicon oxide formed by tetraethyl orthosilicate (TEOS). Moreover, the third and second insulating spacers are removed by buffer oxide etch solution (BOE), and the proportional volume of ammonium fluoric (NH4F) to hydrofluoric (HF) acid in BOE is about 8xcx9c50:1.
Moreover, the first doping regions are doped by arsenic. The second doping regions are doped by phosphorus. The third doping regions are doped by boron.